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STRUCTURE NAME OF PRODUCT
Silicon Monolithic Integrated Circuit DC-AC Inverter Control IC
TYPE FUNCTION
/
20V High voltage process 2CH control with Push-Pull Lamp current and voltage sense feed back control
Sequencing easily achieved with Soft Start Control
Short circuit protection with Timer Latch Under Voltage Lock Out Mode-selectable the operating or stand-by mode by stand-by pin
Automatic Judge function for External synchronization of lamp oscillation BURST mode controlled by PWM and DC input
Absolute Maximum Ratings Parameter Supply Voltage Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Power Dissipation
*1 *2
Symbol VCC Topr Tstg Tjmax Pd
Limits 20 -40+85 -55+150 +150 *1 1063 (BD9240FV) *2 750 (BD9240F)
Unit V mW
Pd derate at 8.5mW/ for temperature above Ta = 25 (When mounted on a PCB 70.0mmx70.0mmx1.6mm)
Pd derate at 6.0mW/ for temperature above Ta = 25 (When mounted on a PCB 70.0mmx70.0mmx1.6mm)
Operating condition Parameter Supply voltage oscillation frequency BCT oscillation frequency Symbol VCC FOUT FBCT Limits 8.0 19.0 30 90 0.05 1.00 Unit V kHz kHz
REV. A
2/4 Electric CharacteristicsTa=25VCC=12V
Limits Parameter WHOLE DEVICE Operating current Stand-by current STAND BY CONTROL Stand-by voltage H 1 Stand-by voltage H 2 Stand-by voltage L UVLO BLOCK Operating voltage (VCC) Hesteresis width (VCC) Operating voltage (UVLO) Hesteresis width (UVLO) SOFT START BLOCK Soft start current SS_COMP detect voltage OSC BLOCK RT Output Voltage STR ON Resistor value BOSC BLOCK BOSC Max voltage BOSC Min voltage BOSC constant current BOSC frequency FEED BACK BLOCK IS threshold voltage 1 IS threshold voltage 2 VS threshold voltage IS source current 1 IS source current 2 VS source current IS COMP detect voltage 1 IS COMP detect voltage 2 VREF input voltage range OUTPUT BLOCK NA output voltage H NB output voltage H NA output voltage L NB output voltage L NA output sink resistance NA output source resistance NB output sink resistance NB output source resistance Drive output frequency CT SYNCHRONOUS BLOCK : CLKIN pin Input High voltage range Input Low voltage range VCT_CLKIN_H VCT_CLKIN_L 2.5 -0.3 5.0 0.5 V V VoutAH VoutBH VoutAL VoutBL Rsink_NA Rsource_NA Rsink_NB Rsource_NB Fout VCC-0.3 VCC-0.3 1.3 4.0 1.3 4.0 57.9 VCC-0.1 VCC-0.1 0.1 0.1 2.5 8.0 2.5 8.0 60.0 0.3 0.3 5.0 16.0 5.0 16.0 62.1 V V V V kHz RT=21k Vis1 Vis2 Vvs Iis1 Iis2 Ivs VISCOMP1 VISCOMP2 VREFIN 1.225 1.220 40 0.64 0.6 1.250 VREFIN 1.250 50 0.66 0.5 1.275 VIS1 1.280 0.9 60 0.9 0.68 1.6 V V V uA uA uA V V V VREFIN1.25V VREFIN=1V No effect at VREF>1.25V DUTY=2.0V DUTY=0V, IS=1.0V VREF applying voltage VBCTH VBCTL IBCT FBCT 1.94 0.40 1.35/BRT 291 2.00 0.50 1.50/BRT 300 2.06 0.60 1.65/BRT 309 V V A Hz (BRT=36.2k, BCT=0.047uF ) fBCT=0.3kHz fBCT=0.3kHz VRT RSRT 1.05 1.50 100 1.95 200 V Iss Vss 1.5 2.3 2.0 2.5 2.5 2.7 uA V Vuvlo Vuvlo Vvlo_u Vvlo_u 6.65 0.37 2.4 0.075 7.00 0.50 2.5 0.100 7.35 0.63 2.6 0.125 V V V V VstH1 VstH2 VstL VCCx0.85 2 0.3 VCC VCCx0.5 0.8 V V V System ON (DUTY 2ch input mode) System ON (DUTY 1ch input mode) System OFF Icc1 Icc2 6.2 21 12.0 60 mA uA FOUT=60kHz, FB=GND Symbol MIN. TYP. MAX. Unit Conditions
REV. A
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FAIL BLOCK : FAIL pin FAIL High voltage FAIL Low voltage TIMER LATCH BLOCK : CP pin VCP ICP 1.91 0.85 2.00 1.05 2.09 1.25 V uA VFAIL_H VFAIL_L 2.95 -0.3 3.1 3.25 0.5 V V
CP timer latch detect voltage CP timer latch charge current COMP BLOCK COMP over voltage detect voltage Hysteresis width COMP PHASE SHIFT BLOCK PH voltage H 1 PH voltage H 2 PH voltage L
VCOMP Vcomp
3.88 0.138
4.00 0.185
4.12 0.232
V V
VSS > 2.4V
VphH1 VphH2 VphL
VCCx0.85 2 0.3
-
VCC VCCx0.5 0.8
V V V
PHASESHIFT PHASESHIFT PHASESHIFT
MODE1 MODE2 MODE3
(This product is not designed to be radiation-resistant.)
Package Dimensions
DEVICE NAME
BD9240FV
BD9240F
Lot No. Lot No.
SOP28 (unit:mm)
CLKIN RT PH BRT BCT DUTY1 DUTY2 VCC
Block Diagram
SSOP-B28 (unit:mm)
STB SS FB1
STB BLOCK
OSC BLOCK SYSTEM ON/OFF PWM1 BLOCK PWM2 BLOCK
BOSC BLOCK
VCC LOGIC BLOCK NA1 NB1
OUTPUT1 BLOCK
IS1 VS1 F/B1 BLOCK
PGND
OUTPUT2 BLOCK FB2 VCC IS2 VS2
NA2 NB2
F/B2 BLOCK
VS1, VS2 IS1, IS2 ADIM BLOCK
PROTECT BLOCK
VCC
UVLO BLOCK
GND
VREF
COMP
CP
SRT
FAIL
UVLO
Pin Description
PIN No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14
PIN NAME
PGND NA2 NB2 UVLO CLKIN SRT RT GND BCT BRT VREF DUTY1 DUTY2 STB
FUNCTION
Power Ground for FET drivers NMOS FET driver (Channel 2 side) NMOS FET driver (Channel 2 side) Input of Under Voltage Lock Out CT Synchronous signal input External resistor between SRT and RT for adjustment frequency of kick-off External resistor between RT and GND for adjustment frequency of saw tooth wave Ground External capacitor between BCT and GND for adjusting the BURST triangle oscillator External resistor between BRT and GND for adjustment frequency of Burst dimming Reference voltage input pin for Error amplifier Control Burst-dimming by PWM signal or DC (Channel 1) Control Burst-dimming by PWM signal or DC (Channel 2) Stand-by switch
PIN No.
15 16 17 18 19 20 21 22 23 24 25 26 27 28
PIN NAME
CP FAIL PH VS2 IS2 FB2 VS1 IS1 FB1 SS COMP VCC NB1 NA1
FUNCTION
External capacitor between CP and GND for timer latch Error Indication output pin Normal : H, Error : L Selector pin for phase shift Error amplifier input 1 (Channel 2) Error amplifier input 2 (Channel 2) Error amplifier output (Channel 2) Error amplifier input 1 (Channel 1) Error amplifier input 2 (Channel 1) Error amplifier output (Channel 1) External capacitor between SS and GND for Soft Start Control and detect the time of Soft Start Input of over voltage detector Power supply input with UVLO Protection NMOS FET driver (Channel 1 side) NMOS FET driver (Channel 1 side)
REV. A
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NOTE FOR USE
This product is produced with strict quality control, but might be destroyed if used beyond its absolute maximum ratings. Once IC is destroyed, failure mode will be difficult to determine, like short mode or open mode. Therefore, physical protection countermeasure, like fuse is recommended in case operating conditions go beyond the expected absolute maximum ratings. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however the variation will be small. Mounting failures, such as misdirection or miscounts, may harm the device. A strong electromagnetic field may cause the IC to malfunction. The GND pin should be the location within 0.3V compared with the PGND pin. BD9240F/FV incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation of the thermal shutdown circuit is assumed. Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave adequate margin for this IC variation. Under operating CP charge (under error mode) analog dimming and burst dimming are not operate. By STB and PH voltage, BD9240F/FV are changed to 3 states. Therefore, do not input STB and PH pin voltage between one state and the other state (0.82.0V, VCCx0.5VCCx0.85 V) By the DUTY1 pin for setting of Burst dimming Mode, When Burst dimming by DC signal do not input DUTY1 voltage between one state and the other state (0.4850.515V, 1.9852.015V) When Burst dimming by PWM signal, set ON time and OFF time of the input PWM pulse signal to more than 30us (Dimming of 0% and Dimming of 100% are no problem) The pin connected a connector need to connect to the resistor for electrical surge destruction. This IC is a monolithic IC which (as shown is Fig.1)has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, (When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) (When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin.
Resistance (PinA) (PinB) C
Transistor (NPN) B E GND
N
P
P N
P P substrate GND Parasitic diode (PinB)
P substrate GND Parasitic diode
N
N
(PinA) B Parasitic diode GND
C E GND
Other adjacent components Parasitic diode
Fig.1 Simplified structure of a Bipolar IC
REV. A
Notice
Notes
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